Various techniques have previously been used to align integrated circuits during the lithography process. A common technique used to fabricate an integrated circuit on a semiconductor device is to build the integrated circuit in layers on a silicon wafer substrate. Each layer corresponds to a process level during fabrication. The circuit design or pattern for each new layer must be placed upon the previous layer within a given spacial tolerance in order for the finished integrated circuit on the semiconductor device to perform its intended function.
Alignment is the term used to describe the placement of one layer of a multiple layered integrated circuit with respect to the other layers of the integrated circuit. One common alignment technique performed during the step and repeat lithography process of building a multiple layered integrated circuit is to use a laser or other light source to scan and detect a mark or illuminate a mark in a previous layer on the wafer. The mark is a typography feature created during the previous step in the lithography process. Alignment of the new layer to a previous layer may be performed by projecting a light source through the projection lens of a step-and-repeat camera or with an off axis light source and detector system.
A detector in the alignment system provides a signal which indicates the location of the previous circuit layer based on the location of the mark. Step and repeat lithography camera systems (frequently referred to as "steppers") use the detector as a ruler or measuring device for correlation of the alignment mark with the location of a previous circuit layer during fabrication of an integrated circuit on a wafer. An alignment check is performed at several locations for the previous layer on the wafer. The data is then used to generate the best grid or stepping pattern for the stepper to use in laying the next circuit layer on the previous circuit layer. The results of the overall alignment of the circuit layers are evaluated after the wafer has been fully exposed and developed.
Prior alignment techniques have worked well in the past for many integrated circuit designs. With the advent of more complex and smaller scale integrated circuits, it has become important to obtain alignment throughout the multiple layers of an integrated circuit on the wafer. Alignment of one layer in the circuit to a previous layer of the circuit must be held to a tight tolerance specification. Alignment of a third layer to the first and second layers must also be held within a tight tolerance. In the current state-of-the-art alignment process, each additional circuit layer is only aligned to marks generated at the previous circuit layer. Therefore, in a multiple layer integrated circuit having up to twenty layers, it is quite possible for alignment between the first and the twentieth layer to be greatly out of tolerance even though each of the individual layers between the first and the twentieth layer is within tolerance. This misalignment frequently results in a failure of the finished product and may substantially reduce the yield of the overall manufacturing process.
A need has thus risen for an alignment system which can be used during the fabrication of a multiple layer integrated circuit to provide alignment between multiple layers of the circuit.